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    • 专利摘要:
    Method for producing a photo-emitting / photo-receiving device (100) with diodes (102), comprising: - producing, on a substrate, a stack comprising first and second doped semiconductor layers; - first etching of the stack, forming first openings crossing the entire thickness of the second layer; - production of dielectric portions (138) covering, in the first openings, lateral flanks of the second layer; - second etching of the stack, extending the first openings until reaching the substrate, delimiting pn junctions of the diodes; - etching extending the first openings in a part of the substrate; - making first electrically conductive portions (148) in the first openings, forming first electrodes of the diodes, and production of second electrodes (150) electrically connected to the second layer; - removal of the substrate, forming a collimation grid (16 0). Figure for the abstract: Figure 1J.
    公开号:FR3090200A1
    申请号:FR1872886
    申请日:2018-12-13
    公开日:2020-06-19
    发明作者:Gabriel Pares
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Description
    Title of the invention: PROCESS FOR PRODUCING A DEVICE WITH PHOTO-EMITTING AND / OR PHOTORECEPTRING DIODES AND WITH A SELF-ALIGNED COLLIMATION GRID
    TECHNICAL AREA AND PRIOR ART
    The invention relates to the field of photo-emitting diode devices, such as light emitting diodes (called LEDs or LEDs, or even micro-LEDs), and / or photo-receiving diodes such as photodiodes. The invention applies in particular to the following field:
    - LED lighting devices, electronic devices comprising arrays of LEDs such as screens, projectors or video walls;
    - electronic or microelectronic photoreceptor devices comprising arrays of photodiodes, such as image sensors;
    - devices comprising both light-emitting diodes and light-receiving diodes, for example forming both a sensor and a screen.
    In devices with photo-emitting and / or photo-receiving diodes, it is advantageous to increase the resolution of these devices, that is to say increase the number of active cells, or pixels, per unit of device surface. This increase in resolution involves both reducing the unit size of the pixels and improving the optical separation of the pixels between them, in particular to reduce the “cross talk” or crosstalk, that is to say the optical interference producing between adjacent pixels. In the case of pixels comprising light-emitting diodes, the increase in their directivity also contributes to the increase in resolution that can be achieved.
    In addition, this increase in resolution must be done by limiting the losses linked to the reception sensitivity and / or the emissivity of the devices, which implies that the reduction in the useful or sensitive surface of the pixels, c that is to say the reception and / or emission surface of the pixels, either accompanied by a reduction in the surface of the peripheral dead zones, that is to say of the surface not emitting or receiving no light, which correspond for example to the regions occupied by the electrodes of the diodes and by the regions of insulation located between and around the pixels. This reduction in the surface of the peripheral dead zones involves minimizing their width around the pixels while maintaining or improving the optical separation between the pixels.
    In current devices, obtaining good performance requires producing an optical pixel separation element, disposed above the emissive and / or receiving face of the pixels. Such an optical pixel separation element, called a collimation grid or a separation grid, makes it possible to avoid parasitic reflections between neighboring pixels and, in the case of a photo-emitting device, to improve the directivity of light emission. .
    Generally, the collimation grid is reported above the pixels, after their completion. In order not to limit the useful area of the pixels and to obtain good performance, the walls forming the collimation grid are produced as thinly as possible, for example with a width less than about 5 μm for pixels each having a useful area whose sides have a dimension (width) equal to approximately 40 μm, and with a significant height, for example greater than approximately 10 μm. Such dimensions lead to the collimating grid having a significant aspect ratio (height / width ratio), for example greater than 2. In addition, the verticality, the low roughness and a good reflectivity of the walls make it possible to obtain a collimation grid which does not disturb the reflection, diffraction and diffusion of the optical signals received and / or emitted by the pixels.
    In the case of a device comprising diodes carrying out photo-emission and / or photo-reception from their front face (face opposite to that located on the side of the substrate on which the diodes are made), such a collimation grid can be performed during the manufacture of the interconnection levels, also called BEOL (“Back-End Of Line”), of the device. One of these interconnection levels, formed on the side of the front face of the diodes, can be dedicated to the production of the collimation grid. This configuration provides a high degree of integration, and therefore a small footprint, as well as good alignment of the collimation grid with the pixels. However, this configuration is not applicable to a device performing a light emission and / or reception from the rear face of the diodes because the interconnection levels are made on the front face of the device. In addition, the height of the collimation grid thus obtained is limited by the techniques used to achieve the interconnection levels, this height generally being between approximately 1 μm and 3 μm.
    In the case of a device producing a light emission and / or reception from its rear face, the collimation grid is therefore produced by a specific process implemented after the achievement of the interconnection levels, the postponement of the device on a support and removing the substrate from which the device is made. The withdrawal of the substrate frees the rear face of the diodes on which the collimating grid is produced. The main problems to manage are in this case the alignment of the collimation grid with the pixels, and the realization of the collimation grid with an important form factor.
    When the collimating grid is transferred simultaneously to the rear faces of several emission and / or reception devices transferred to the same support (transfer to the scale of the substrate, or "wafer level"), before cutting of the support making the devices unitary, the alignment accuracy obtained can be less than about 1 μm. On the other hand, the alignment must take into account a possible deformation of the devices that may appear after removing the substrates from which the devices are made. In addition, the steps implemented to produce the collimation grid may be subject to constraints related in particular to the technique used to transfer the devices to their support, such as for example temperature constraints not to be exceeded or constraints on the chemicals that can be used without damaging the bonding interface between the devices and the support.
    When the collimation grid is produced on a unitary light emission and / or reception device, for example of millimeter size, transferred to a support corresponding for example to an active circuit of the ASIC (“Application-Specific Integrated”) type Circuit ", or integrated circuit specific to an application) by means of electrical connections of the type, for example, micro-pillar or micro-ball, it is difficult to obtain a good alignment between the collimation grid and the pixels because the techniques microelectronics are no longer usable for the production of the collimation grid. It is also difficult to produce the collimation grid with a large form factor taking into account the methods applicable to this scale and the topology of the device. Furthermore, the collimation grid cannot be produced on the device before it is transferred to the support because on the one hand it is necessary to secure the device to the support before removing the substrate to keep good mechanical stability of the assembly , and on the other hand the topology created by the collimation grid would make it very difficult to transfer the device to its support. To produce a collimation grid on a unitary light emission and / or reception device, it is possible to reconstitute a plate from the devices previously transferred to their supports (for example diodes each assembled on a chip CMOS), in order to allow the use of microelectronics techniques capable of achieving the alignment performance and the resolution necessary for producing the collimation grid. Such a method involves securing the devices and their supports on a plate, then making a flat surface by embedding them in an encapsulation material without damaging the devices. The collimation grid is then produced by lithography on the rear faces of the devices. In this case, it is however necessary to take into account the misalignment of the devices linked to their individual transfer to the plate and to the reconstruction process, this misalignment possibly being in the end by several microns. In addition, a collar screen having a height of several microns and a form factor greater than 2 requires a complicated lithography process requiring very sophisticated equipment.
    STATEMENT OF THE INVENTION
    An object of the present invention is to provide a solution for optically separating the adjacent pixels from a photo-emitting and / or photo-receiving device on the rear face while minimizing the area occupied on the device to achieve this, offering good alignment between the pixels and the collimation grid used to achieve this optical separation, which is compatible with the production of a collimation grid having a high aspect ratio, for example greater than or equal to 2, and which can d '' apply to unitary devices or to several devices arranged on the same support.
    For this, the present invention provides a method for producing at least one photo-emitting and / or photo-receiving diode device, comprising at least: - production, on a substrate, of a stack of layers comprising at least first and second layers of semiconductors doped with opposite conductivity types, the first layer being disposed between the substrate and the second layer;
    - first etching of the stack from a front face of the stack located on the side opposite to that disposed against the substrate, forming first openings crossing the entire thickness of the second layer and whose bottom walls are formed by the first layer;
    - Production of dielectric portions covering, in the first openings, lateral flanks formed at least by the second layer;
    - second etching of the stack, extending the first openings through a remaining thickness of the first layer until reaching the substrate, the first openings delimiting portions of the first and second layers forming p-n junctions of the diodes;
    - etching extending the first openings in part of the substrate;
    - Production of first electrically conductive portions arranged in the first openings and in electrical contact with lateral sides of the portions of the first layer, forming first electrodes of the diodes, and production of second electrodes electrically connected to the portions of the second layer;
    - removal of the substrate, revealing a rear face of the stack of layers forming an emissive face of each of the diodes and releasing parts of the first electrically conductive portions forming a collimation grid.
    With this method, the collimating grid and the first diode electrodes are formed by the same elements (the first electrically conductive portions), using, for their production, the substrate from which the diodes are produced. Thus, the collimating grid is self-aligned with the first electrodes of the diodes, which limits the optical losses within the device and eliminates the problems of alignment of the collimating grid with respect to the diodes encountered in the methods. of the prior art. This also makes it possible to reduce the dimensions of the dead zones within the device since no surface is lost due to a misalignment between the collimation grid and the pixels.
    In this method, the elements forming the collimation grid are produced before the removal of the substrate, which avoids the problems linked to a possible deformation of the diodes which may appear after having removed the substrate, and removes the constraints linked to the technique. used to transfer the devices to their support since the elements of the collimation grid are produced before the substrate is removed.
    This method also has the advantage of allowing the collimating grid to be produced with a very favorable geometry in order to obtain good optical insulation performance between the pixels and low spurious reflections between the pixels. The collimating grid can in particular be produced such that the parts of the first electrically conductive portions forming this grid have a form factor for example greater than 2, or advantageously greater than or equal to 4.
    This method also offers great freedom regarding the geometry with which the elements of the collimation grid are made, because the shape of the parts of the first electrically conductive portions forming the collimation grid is defined by the shape of the first openings made in the substrate which can be easily adapted according to needs.
    This method also has the advantage of being able to be implemented on the scale of the substrate by microelectronics techniques with great precision, great robustness and great reproducibility, but also for unitary devices.
    This method advantageously combines the production of the collimating grid with an efficient production of the electrodes of the diodes and contributing to the optimization of the useful surface of the diodes.
    In addition, the collimation grid thus produced does not have any discontinuity with the first electrodes of the diodes, which leads to better mechanical strength of the collimation grid on the diodes, a weaker cross-talk, and a reduction of stray reflections within the device.
    The simultaneous production of the collimation grid and the first electrodes of the diodes also makes it possible to reduce the total number of steps to be implemented to produce the collimation grid and the first electrodes of the diodes.
    This method applies to the production of a device, the diodes of which provide photo-emission and / or photo-reception from a rear face of the stack of layers (face located on the side of the substrate on which the stack of layers is arranged). The diodes can be electrically interconnected at their front faces.
    When the unintentionally doped semiconductor is present between the first and second layers, the diode junctions correspond to p-i-n junctions.
    The part of the substrate in which the etching extending the first openings is implemented can have a thickness of between 1 μm and 20 μm. This depth can correspond to the height of the collimation grid obtained. Advantageously, the part of the substrate in which the etching extending the first openings is carried out may have a thickness greater than 3 μm in order to obtain a collimation grid with a height greater than 3 μm.
    A ratio between the thickness of the part of the substrate in which the etching extending the first openings is implemented and a smaller dimension of each first opening in a plane parallel to an interface between the substrate and the stack of layers (this smallest dimension corresponding to the width of the parts of the first electrically conductive portions forming the collimation grid), corresponding to the aspect ratio of parts of the first electrically conductive portions forming the collimation grid, can be greater than or equal to 2, or even advantageously greater than or equal to 4.
    The first etching of the stack can be implemented such that the first openings also pass through part of the first layer, and the dielectric portions can be produced such that they cover, in the first openings, lateral flanks of said part of the first layer. This configuration allows good electrical insulation to be formed between the first electrodes and the second semiconductor layer.
    The method can be such that:
    the stack comprises a dielectric mask forming the front face of the stack,
    the first and second etchings of the stack are implemented through the dielectric mask such that the first openings also pass through the dielectric mask, and
    - The dielectric portions also cover, in the first openings, lateral flanks of the dielectric mask.
    This dielectric mask also contributes to the achievement of good electrical insulation between the first and second electrodes at the front faces of the diodes.
    The second etching of the stack can be carried out such that the lateral flanks of the dielectric portions are aligned with the lateral flanks of the portions of the first layer.
    The method may further comprise, between the second etching of the stack and the production of the first electrically conductive portions, the production of second openings passing through the dielectric mask and in which the second electrodes can be at least partially produced.
    The first and second electrodes can be produced by depositing at least one electrically conductive material in the first and second openings and on the dielectric mask, then by implementing a planarization step of the electrically conductive material with stopping on the dielectric mask .
    The stack may further include an electrically conductive layer such that the second layer is disposed between the electrically conductive layer and the first layer, and the first etching of the stack can be implemented such that the first openings pass through the electrically conductive layer and delimit portions of the electrically conductive layer forming a part of each of the second electrodes.
    The method may further comprise, between the production of the first electrically conductive portions and the removal of the substrate, the implementation of a transfer of the stack and the substrate on a support such that the stack is disposed between the substrate and the support. In such a configuration, the front face of the stack is arranged opposite the support.
    The postponement of the stack and of the substrate can be implemented with electrically conductive connection elements electrically connecting the first and second electrodes of the diodes to the support during the implementation of the postponement of the stack and of the substrate on the support.
    The substrate removal step can be implemented collectively for several photo-emitting and / or photo-receiving diode devices each comprising a stack and a substrate transferred onto a support, and the supports of the photo-diode devices emitters and / or photoreceptors can be joined on a holding plate before the implementation of the step of removing the substrate.
    The first openings can be made such that they form a grid pattern surrounding each of the diodes.
    The etching steps can be implemented such that each of the first openings defining pn junctions of light emitting diodes has a smaller dimension, at the level of a bottom wall formed in the substrate, which is less than a smaller dimension of the first opening at an interface between the substrate and the stack, and / or each of the first openings delimiting pn junctions of light-receiving diodes has a smaller dimension, at the level of the wall of bottom formed in the substrate, which is greater than the smallest dimension of the first opening at the interface between the substrate and the stack. Such a configuration is favorable for improving the directivity of emission of the light-emitting diodes and reducing the cross-talk between light-emitting diodes.
    The method may further comprise, after the step of removing the substrate, the implementation of a step of depositing at least one anti-reflection and / or metallic layer on the collimation grid, and / or the implementation of a treatment increasing the roughness of the collimation grid. Such steps can improve the optical qualities of the collimation grid.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which:
    -FIG. IA, FIG. IB, FIG. IC, FIG. ID, FIG. IE, FIG. 1F, FIG. IG, FIG. 1H, FIG. II and FIG. IJ represent the steps of a method for producing a photo-emitting and / or photo-receiving diode device according to a particular embodiment;
    -FIG. 2 shows an intermediate structure obtained during the implementation of a method for producing a photo-emitting and / or photo-receiving diode device according to an alternative embodiment.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to the other.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Figures IA to IJ show the steps of a method for producing a device 100 with photo-emitting and / or photo-receiving diodes according to a particular embodiment. In this embodiment, the device 100 comprises several diodes 102 forming at least one matrix of diodes and serving as matrix (s) of pixels of the device 100. As a variant, the diodes 102 can be produced one beside the other without forming an array of diodes, that is to say without regular spacing between them. According to another variant, the device 100 may have only a single diode 102. In addition, in the particular embodiment described below, the diodes 102 correspond to photo-emitting diodes, here LEDs.
    As shown in Figure IA, the device 100 is made from a substrate 104 comprising for example sapphire and / or silicon and / or a semiconductor for example similar to that used to form the active part diodes 102, and / or carbon silicide and / or glass and / or any other material allowing the substrate 104 to form a growth substrate allowing the production of the semiconductor stack forming the active part of the diodes 102. The substrate 104 serves as a support for the deposition and / or growth of layers intended for producing the diodes 102 of the device 100.
    A stack 106 of layers is formed on the substrate 104. This stack 106 comprises materials from which the diodes 102 will be produced.
    The stack 106 comprises a first layer 108 of semiconductor doped according to a first type of conductivity, for example of the n type, deposited on the substrate 104. In the particular embodiment described here, this first layer 108 corresponds to a superposition of several distinct layers of semiconductor, for example a layer 110 of n + doped semiconductor with a concentration of donors for example between approximately 5.10 17 and 5.10 20 donors / cm 3 on which is placed another layer 112 of n- doped semiconductor with a donor concentration for example of between approximately 10 17 and 5.10 19 donors / cm 3 . For example, layer 110 comprises GaN and layer 112 comprises InGaN. The thickness of layer 110 is for example greater than approximately 100 nm, and here equal to approximately 3 μm, and that of layer 112 is for example between approximately 5 nm and 500 nm. The total thickness of the first layer 108, that is to say the sum of the thicknesses of the layers 110 and 112 in the example described here, is for example between approximately 20 nm and 10 μm, and preferably between about 2 pm and 4 pm. The layer 110 here forms a buffer layer placed between the layer 112 and the substrate 104 and is used in particular to filter the growth defects of the layer 112 so that these defects are not found in the layer 112.
    As a variant, the layers 110 and 112 can be doped with the same level of n-type doping (unlike the case described above where the layer 110 is doped n + and the layer 112 is doped n-).
    According to another variant, the first layer 108 may correspond to a single layer of n-doped semiconductor, and with a concentration of donors for example between approximately 10 17 and 5.10 20 donors / cm 3 , comprising for example GaN and whose thickness is for example between about 20 nm and 10 pm, and advantageously between about 2 pm and 4 pm.
    The stack 106 also includes one or more emissive layers 114, for example five emissive layers 114, each intended to form, in the diodes 102, a quantum well. In FIG. 1A, only three emissive layers 114 are shown. The emissive layers 114 comprise for example InGaN. Each of the emissive layers 114 is arranged between two barrier layers (not visible in FIGS. IA - IJ), comprising for example GaN. The emissive layers 114 are arranged on the first layer 108. The emissive layers 114 comprise so-called intrinsic semiconductor materials, that is to say unintentionally doped (of concentration in residual donor nest for example equal to approximately 10 17 donors / cm 3 , or between approximately 10 15 and 10 18 donors / cm 3 ). The thickness of each of the emissive layers 114 is for example equal to approximately 3 nm and more generally between approximately 0.5 nm and 10 nm, and the thickness of each of the barrier layers is for example between approximately 1 nm and 25 nm.
    The stack 106 also includes a second layer 116 of semiconductor doped according to a second type of conductivity, opposite to that of the doping of the first layer 108 and therefore here of type p, with a concentration of acceptors for example between about 10 17 and 5.10 19 acceptors / cm 3 . The second layer 116 is arranged on the emissive layers 114. The first and second layers 108 and 116 (and more particularly the layers 112 and 116 in the example described here) are intended to form the pn junctions of the diodes 102. The semi conductor of the second layer 116 is for example GaN and its thickness is for example between approximately 20 nm and 10 μm.
    In an alternative embodiment, an electron blocking layer (not visible in FIG. IA) can be arranged between the second layer 116 and the emissive layers 114, this electron blocking layer comprising for example l 'AIGaN with for example about 12% of aluminum and p-doped with a concentration of acceptors for example equal to about 1.10 17 acceptors / cm 3 .
    Materials other than those mentioned above can be used to make the diodes 102.
    The stack 106 also includes an electrically conductive layer 118 intended to form, in each of the diodes 102, part of a second electrode (corresponding to the anode in the example described here) which will be in contact with the semiconductor of the second layer 116. The electrically conductive layer 118 is disposed on the second layer 116. The electrically conductive material used is for example optically reflective, and corresponds for example to aluminum.
    Finally, the stack 106 also includes a layer 120 intended to form a dielectric hard mask, disposed on the electrically conductive layer 118. The material of this layer 120 is for example Si0 2 . The upper face of the layer 120 here forms a front face 122 of the stack 106, this front face 122 being on the side opposite to that disposed against the substrate 104.
    A first etching of the stack 106 is implemented from the front face
    122 of the stack 106 to form, in the stack 106, first openings 124 which will then be used to make the first electrodes (corresponding to the cathodes in the example described here) of the diodes 102 as well as the collimation grid of the device 100.
    This first etching is first carried out in the layer 120 to form a dielectric mask 126 which will serve as an etching mask for the etching of the other layers of the stack 106. The pattern formed by the first openings 124 in the dielectric mask 126 corresponds to that of the first electrodes of the diodes 102 and of the collimating grid. The first openings 124 are also intended to delimit portions of the first and second layers 108 and 116 forming the pn junctions of the diodes 102. In the embodiment described here, the diodes 102 are produced in the form of mesa structures, or structures in islets. In addition, in the particular embodiment described here, the cathodes of the diodes 102 form a cathode common to several diodes 102, or to all the diodes 102, of the device 100.
    An etching of the electrically conductive layer 118 is then implemented according to the pattern of the dielectric mask 126. Remaining portions 128 of the layer 118 are intended to form parts of the second electrodes of the diodes 102.
    An etching of the second layer 116 is then implemented according to the pattern of the dielectric mask 126, forming portions 130 of doped semiconductor intended to form part of the p-n junctions of the diodes 102 (see FIG. 1B). The layers 116, 118 and 120 are for example etched by the implementation of reactive ion etching by a plasma torch system, or ICP-RIE for "Inductively Coupled Plasma Reactive Ion Etching".
    As shown in Figure IC, the first openings 124 are extended by etching in the emissive layers 114 and in part of the thickness of the first layer 108, always according to the pattern defined by the dielectric mask 126. This etching is stopped at a depth level located in the first layer 108 and such that the bottom walls of the first openings 124 are formed by the first layer 108. In the example described here, the etching is stopped at a level located in the layer 112 such that layer 110 and part of the thickness of layer 112 are not etched. The thickness, referenced “b” in FIG. 1C, of the layer 112 which is etched is for example between approximately 100 nm and 5 μm. The remaining thickness of the layer 112 denoted “e” therefore results from the choice of the initial thicknesses of the layers 110 and 112 and of the depth of the etching in the layer 112. The choice of the etching depth produced, and therefore of the remaining thickness of the first layer 108 in the bottom of the first openings 124, depends in particular on the initial thickness of the first layer 108 (and therefore on the initial thicknesses of the layers 110 and 112 in the embodiment described here) and this so that the remaining thickness of the first layer 108 is sufficient to make good electrical contact between the semiconductor (s) of the first layer 108 and the first electrodes of the diodes 102 which will be produced subsequently in the first openings 124.
    Alternatively, this etching can be stopped at the upper face of the layer 110 such that this layer 110 is not etched but that the entire thickness of the layer 112 is etched. According to another variant, this etching can be stopped at a level located in the layer 110 such that, in the first layer 108, only part of the thickness of the layer 110 is not etched. These two variants can be envisaged when the material of the layer 110 is suitable for forming, with the material of the layer 116, the p-n junctions of the diodes 102.
    The remaining portions of the emissive layer or layers 114 form active areas 132 of the diodes 102. This first etching also forms portions 134 of portions 136 of doped semiconductor intended to form, with the portions 130, the pn junctions (pin junctions in the example described here, due to the presence of the emissive layers 114 between the first and second layers 108, 116) of the diodes 102 (in FIG. 1C, the parts 134 are symbolically delimited from the rest of the portions 136 by dotted lines).
    A dimension, referenced "a" in Figure IC, the first openings 124 corresponding to the distance between two mesa structures of neighboring diodes 102 is for example greater than or equal to about 50 nm, the minimum distance between two neighboring diodes 102 being defined by the minimum resolution of the lithography used. This dimension “a” corresponds to the sum of the width of a portion of electrically conductive material which will be produced between the two mesa structures of the diodes 102 to form a cathode common to these diodes 102 and the thicknesses of two vertical dielectric portions which will be also arranged between the two mesa structures of the diodes 102. Thus, the dimension “a” depends on the width of the cathode produced between the diodes 102 which is chosen in particular as a function of the acceptable losses linked to the supply of the electric current in the areas furthest from peripheral contact points. The etching implemented is a dry etching, for example by a plasma based on Cl 2 or an RIE etching, for example ICP-RIE.
    The dimensions of the sides of one of the mesa structures can be between approximately 500 nm and 1 mm, or between 500 nm and several millimeters, depending on the intended applications. For applications using high power diodes (for example LED bulbs to form car headlights), the dimensions of the diodes 102 will be larger than for applications using lower power diodes 102.
    A dielectric layer, for example corresponding to a bilayer
    SiN / SiO 2 , and forming a passivation layer, is then deposited with a conforming thickness, for example between approximately 5 nm and 1 μm and advantageously equal to approximately 200 nm, on the dielectric mask 126 and along the walls of the first openings 124, thus covering the side walls of the dielectric mask 126, electrically conductive portions 128, semiconductor portions 130, active areas 132 and portions 134 of the portions 136. The dielectric layer is also deposited on the non-etched portions of the first layer 108 forming the bottom walls of the first openings 124. This dielectric layer is for example formed by a PECVD (chemical vapor deposition assisted by plasma) or ALD (atomic layer deposition) type depending on the nature of the or deposited materials.
    Anisotropic etching, for example dry etching such as RIE etching, is then implemented such that the parts of the dielectric layer being in the first openings 124 and not covering the side walls of the mesa structures of diodes 102 are removed, thus revealing the parts of the first layer 108 located at the bottom of the first openings 124. The parts of this dielectric layer covering the upper face of the dielectric mask 126 are also removed. Thus, only portions 138 of the dielectric layer covering the side walls of the dielectric mask 126, electrically conductive portions 128, semiconductor portions 130, active areas 132 and portions 134 of the semiconductor portions 136 are retained. in the first openings 124.
    As shown in Figure 1D, a second etching of the stack 106 is implemented, extending the first openings 124 through the remaining thickness of the first layer 108 of semiconductor until reaching the substrate 104 , that is to say until the bottom walls of the first openings 124 are formed by the substrate 104. This second etching makes it possible to delimit the portions of semiconductor 136 therebetween and completes the formation of the mesa structures. diodes 102. This second etching reveals lateral flanks 140 of the portions 136 which will form electrical contact zones for the first electrodes of the diodes 102.
    At the end of this second etching, the portions of the dielectric mask 126, the electrically conductive portions 128, the semiconductor portions 130 and 136, the active areas 132 and the dielectric portions 138 form mesa structures, c that is to say stacks in the form of islands, arranged on the substrate 104. Each mesa structure of each diode 102 has a section, in a plane parallel to the face of the substrate 104 on which these structures rest, for example in disc shape. Each of the mesa structures can therefore form a cylindrical island. Mesa structures of different shape can be envisaged, for example in the form of a paving stone.
    Another anisotropic etching step, for example of the RIE or DRIE type and selective with respect to the materials of the diodes 102 other than that or those of the substrate 104, is implemented to extend the first openings 124 through part of the thickness of the substrate 104, called “c” in FIG. 1E.
    First electrically conductive portions are intended to be made in the first openings 124 to form the first electrodes of the diodes 102 as well as the collimating grid of the device 100. The depth "c" of the parts of the first openings 124 in the substrate 104 corresponds to the height of the collimation grid which will be obtained at the end of the process. The value of this depth “c” thus depends on the type of diodes 102 and on the desired separation and / or focusing performance. For example, when the diodes 102 correspond to LEDs, the depth "c" is for example between approximately 1 μm and 20 μm, and advantageously greater than or equal to approximately 10 μm. For example, for pixels having sides of dimension equal to 40 μm, the depth “c” is for example equal to 10 μm.
    Considering that the thickness of each of the portions 138 is called "d", the width, or more generally the lateral dimension, of each of the first openings 124 in the substrate 104 is equal to "a - 2d". The dimensions a, c and d are therefore chosen such that the form factor (height / width) of the first openings 124 is advantageously greater than or equal to 2, or even greater than or equal to 4.
    Second openings 142 are then produced through the dielectric mask 126, forming locations for the production of the second electrodes of the diodes 102 (FIG. 1E). These second openings 142 pass through the entire thickness of the dielectric mask 126 so that the bottom walls of the second openings 142 are formed by the electrically conductive portions 128. This etching is for example of the ICP-RIE type.
    A first electrically conductive material 144 is then deposited in the first and second openings 124, 142 as well as on the dielectric mask 126 (FIG. IL). This first electrically conductive material 144 is deposited in a conforming manner, that is to say by forming a layer of substantially constant thickness on the dielectric mask 126 and along the side walls and the bottom walls of the first and second openings 124 , 142. In the embodiment described here, the first electrically conductive material 144 is formed by the deposition, for example of the PVD type, of a first layer of titanium with a thickness for example of between approximately 5 nm and 300 nm , followed by a deposition, for example PVD, of a second layer of aluminum with a thickness for example of between approximately 50 nm and 1 μm. The deposition techniques used are chosen so that they are adapted to the large form factor of the volumes formed by the first openings 124, and correspond for example to those used to deposit the electrically conductive material or materials of the conductive vias or TSV (“Through-Silicon Via”). The first electrically conductive material 144 is in electrical contact with the lateral flanks 140 of the semiconductor portions 136 in the first openings 124, and with the portions 128 at the bottom walls of the second openings 142.
    As shown in Figure IG, a second electrically conductive material 146 is deposited by filling the remaining volumes of the first and second openings 124, 142. In Figure IG, the thickness of this second electrically conductive material 146 is such that 'it also covers the parts of the first electrically conductive material 144 disposed on the dielectric mask 126. The second electrically conductive material 146 is for example copper which can be formed by the implementation of an electrochemical deposit (ECD or "Electro- Chemical Deposition ”) full plate, that is to say on the whole of the structure previously produced.
    The diodes 102 of the device 100 are completed by implementing a chemical mechanical planarization (CMP) in order to remove the portions of the first and second electrically conductive materials 144 and 146 which protrude from the first and second openings 124, 142 (see Figure 1H). This planarization makes it possible to electrically isolate the electrically conductive materials present in the first openings 124 from those arranged in the second openings 142.
    The electrically conductive materials present in the first openings 124 form first electrically conductive portions 148 extending over the entire height of the mesa structures of the diodes 102, which are electrically connected to the semiconductor portions 136 only at the flanks side 140, and which extend into the substrate 104. The parts of these first electrically conductive portions 148 located at the mesa structures of the diodes 102 form the first electrodes of the diodes 102, and the parts of these first electrically conductive portions 148 are found in the layer 108 and in the substrate 104 are intended to form the collimation grid of the device 100.
    The electrically conductive materials present in the second openings 142 form second electrically conductive portions 150 corresponding to the second electrodes of the diodes 102, each in electrical contact with one of the semiconductor portions 130 via a electrically conductive portions 128.
    The structure obtained comprises an upper face 147 which is substantially planar, formed by the upper faces of the first and second electrically conductive portions 148, 150, dielectric portions 138 and the dielectric mask 126. This face 147 corresponds to the front face diodes 102 at which electrical connections with the electrodes will be made.
    Thanks to the vertical dielectric portions 138, the first electrically conductive portions 148 are electrically well insulated from the semiconductor portions 130 and from the active zones 132. The thickness “d” of the dielectric portions 138 can be chosen such that a current of acceptable leakage is tolerated on each of the diodes 102, for example less than approximately 1% of the nominal current passing through the diode 102, when they are subjected to a potential difference (applied between the cathode and the anode) for example order of 4 Volts. The minimum thickness of the dielectric portions 138 is for example between approximately 3 nm and 5 nm, or between 3 nm and 4 nm, depending on the material or materials used to produce the dielectric portions 138.
    In order to guarantee electrical insulation between the first and second electrodes of the diodes 102, and to avoid the presence of electrically conductive materials 144 and 146 on the face 147 which could create a short circuit between two electrodes, the planarization step is advantageously implemented until an over-etching of the first and second electrically conductive portions 148, 150 is made with respect to the dielectric materials of the portions 138 and of the dielectric mask 126, forming in the first and second electrically conductive portions 148, 150 hollow at the upper faces of these portions. These recesses can have a depth, with respect to the plane of the upper face 147, of between approximately 5 nm and 150 nm. This over-etching can be obtained by playing on the etching anisotropy and thanks to the etching selectivity which exists between the dielectric materials of the portions 138 and of the mask 126 and the materials of the electrically conductive portions 148, 150. work has a different abrasion speed depending on the materials, and in the process described here, the abrasion of the materials of the electrically conductive portions 148, 150 is faster than that of the dielectric materials of the portions 138 and of the mask 126. This is translated, at the level of the upper face 147, by a withdrawal of the materials from the electrically conductive portions 148, 150 with respect to the dielectric portions 130 and to the dielectric mask 118. Thus, the electrodes of the diodes 102 remain perfectly isolated from one another thanks to an intrinsic property of the planarization implemented. Such over-etching can also be implemented by an RIE etching process.
    In the embodiment described above, the semiconductor portions 136 are n-type and the semiconductor portions 130 are p-type. Alternatively, the semiconductor portions 136 may be p-type and the semiconductor portions 130 may be n-type. In this variant, the first electrically conductive portions 148 form the anodes of the diodes 102 and the second electrically conductive portions 150 form, with the conductive portions 128, the cathodes of the diodes 102.
    The substantially flat surface obtained at the level of the upper face 147 makes it easy to hybridize the diode array 102 produced on any type of support such as an electronic circuit. For example, it is possible to carry out a hybridization between the matrix of diodes 102 and a support corresponding to an electronic circuit by direct bonding (“direct bonding”, also called bonding by molecular adhesion) of the matrix of diodes 102 to the electronic circuit, or by using electrical connection elements between the diode array 102 and the electronic circuit. Details of the implementation of a direct bonding are for example described in the document "Mechanisms of copper direct bonding observed by in-situ and quantitative transmission electron microscopy" by M. Martinez et al., Thin Solid Films 530 (2013) 96-99.
    In the non-limiting example of embodiment shown in FIG. II, the diode array 102 is transferred onto a support 152 comprising electrical connection elements 154 to which the first and second electrodes of the diodes 102 are electrically connected. The face 147 of the array of diodes 102, corresponding to the front faces of the diodes 102, is arranged opposite the support 152. The electrical connection elements 154 correspond for example to balls of fusible alloy (comprising for example SnAg and / or indium), or copper pillars covered with solder material, or micro-inserts, or micro-tubes.
    This support 152 may correspond to an electronic circuit, comprising for example CMOS electronic components, on which the diode array 102 is transferred and to which the diode array 102 is electrically connected. Such an electronic circuit can in particular be used to electrically control the diodes 102 corresponding for example to light-emitting diodes and / or to process the signals delivered by the diodes 102 corresponding for example to photodiodes. As a variant, the support 152 can correspond to a passive element not comprising electronic components, such as for example a card or an organic substrate.
    In the embodiment shown in Figure II, connection pads 156 of UBM type (for "Under Bump Metallization") are made on the face 147, against the first and second electrodes of the diodes 102, before the transfer of the diodes to the support 152. These connection pads 156 ensure good electrical contact between the first and second electrodes of the diodes 102 and the electrical connection elements 154.
    During the transfer of the diode array 102 on the support 154, the presence of the substrate
    104 ensures sufficient mechanical rigidity for handling and securing the diode array 102 to the support 154.
    After this postponement, the substrate 104 is removed, thereby releasing the rear faces 158 of the diodes through which the light is intended to enter or exit depending on whether the diodes 102 are photo-emitting or photo-receiving diodes. The techniques for removing the substrate 104 which are implemented must take into account the presence of the parts of the first electrically conductive portions 148 located in the substrate 104 and which are intended to form the collimation grid. Thus, the removal process implemented is selective with respect to the material (s) of the first electrically conductive portions 148 present in the substrate 104. For example, it is possible to remove at first a portion of the thickness of the substrate 104, in which the first electrically conductive portions 148 do not extend, by the implementation of a non-selective method, for example by lapping, then removing the remaining portions of the substrate 104 so selective, for example by chemical or physical etching. It is also possible to remove the substrate 104 by laser peeling ("laser lift-off"). When the substrate 104 comprises sapphire, this substrate 104 can be removed by RIE plasma etching. The technique or techniques used to remove the substrate 104 are adapted as a function of the material of the substrate 104.
    The structure obtained after the removal of the substrate 104 is shown in Figure IJ. The parts of the first electrically conductive portions 148 released from the substrate 104 form at least partially the collimation grid 160 of the device 100.
    Optionally, after removing the substrate 104, it is possible to deposit one or more layers of material (x) on the collimation grid 160 and / or to carry out one or more surface treatments of the collimation grid 160. For example, it is possible to implement a treatment aimed at improving the performance of the collimation grid 160. This treatment may include the deposition of a metallic material on the collimation grid 160, improving the optical qualities of the collimation grid 160 such as for example the anti-reflection properties of the collimation grid 160. This treatment (for example an etching) can also increase the roughness of the collimation grid 160. This treatment can be selective or not with respect to the rear faces 158 of diodes 102.
    In the particular embodiment described above, the device 100 advantageously comprises a matrix of diodes 102 which are light-emitting diodes, the microelectronic device being able to form part of an LED display device (screens, projector, video wall, etc.). This matrix of diodes 102 comprises the first electrically conductive portions 148 which form a cathode common to all the diodes 102, and each diode 102 comprises a second electrically conductive portion 150 forming an anode making it possible to carry out the individual addressing of each of the diodes 102 .
    Alternatively, the microelectronic device 100 may include a matrix of diodes 102 which are photo-receiving diodes, or photodiodes. In this variant, the anodes and cathodes of the diodes 102 are not used to supply current to the diodes 102 but are used to recover the currents photo-generated by the diodes 102.
    According to another variant, whether the diodes 102 correspond to light-emitting diodes or to photodiodes, the mesa structures of the diodes 102 may not include layers between the doped semiconductor portions 130 and 136 (corresponding to the active zones emissive or to intrinsic semiconductor portions), and the p and n doped semiconductors are then placed directly against each other.
    In the particular embodiment described above, the first electrically conductive portions 148 are produced such that the parts forming the collimating grid 160 have lateral flanks substantially perpendicular to the rear faces 158 of the diodes 102. As a variant, it is possible that the angles formed between these lateral flanks and the rear faces 158 of the diodes 102 are not equal to 90 °.
    For example, when the diodes 102 correspond to light-emitting diodes, the first openings 124 can be made such that their width, at their bottom walls located in the substrate 104, is less than their width at the level of an interface between the substrate 104 and the stack of layers forming the pn junctions of the diodes 102. This profile of the first openings 124 is therefore found on the parts of the first electrically conductive portions 148 forming the collimation grid 160. This particular profile of the collimation grid 160 is advantageous when the diodes 102 correspond to light-emitting diodes because such a collimation grid makes it possible to reduce the stray reflections of the light emitted by the diodes 102.
    When the diodes 102 correspond to photo-receiving diodes, the collimation grid 160 can be produced with a profile opposite to that described above, that is to say such that the width of the first electrically conductive portions 148, at the bottom walls located in the substrate 104, ie greater than their width at the interface between the substrate 104 and the stack of layers forming the pn junctions of the diodes 102. This particular profile of the grid collimation 160 is advantageous when the diodes 102 correspond to photodiodes because such a collimation grid 160 makes it possible to reduce the cross-talk effect between the diodes 102.
    According to an alternative embodiment, after having removed the substrate 104, it is possible to partially etch the layer 110, over part of its thickness, in order to increase the height of the parts of the first electrically conductive portions 148 forming the grid. collimation 160.
    According to an alternative embodiment, the step of removing the substrate 104 and possibly of the partial etching of the layer 110 can be implemented collectively for several devices 100. As shown in FIG. 2, several devices 100 each comprising the diodes 102 transferred to the support 152 but also comprising the substrate 104 are transferred to a retaining plate 200, and are for example held on this plate by means of a layer of temporary glue 202. In the example shown on FIG. 2, the devices 100 are protected by an encapsulating material 204, comprising for example a polymer, formed around the devices 100 but not covering the substrates 104 of the devices 100 so that these substrates 104 are accessible. The substrates 104 of the devices 100 can then be removed using the techniques described above, and this without risk of damaging the diodes 102 thanks to the presence of the encapsulating material 204. After having removed the substrates 104, the encapsulating material 204 is withdrawn, for example by dissolution, and the devices 100 are detached from the retaining plate 200. As a variant, a step of processing the collimation grids 158 of the devices 100 can be implemented collectively before removing the encapsulating material 204.
    权利要求:
    Claims (1)
    [1" id="c-fr-0001]
    Method for producing at least one photo-emitting and / or photo-receiving diode (102) device (100), comprising at least: - production, on a substrate (104), of a stack (106) of layers comprising at least first and second layers (108, 116) of semiconductors doped with opposite conductivity types, the first layer (108) being disposed between the substrate (104) and the second layer (116);
    - First etching of the stack (106) from a front face (122) of the stack (106) being on the side opposite to that disposed against the substrate (104), forming first openings (124) crossing the entire thickness of the second layer (116) and of which bottom walls are formed by the first layer (108);
    - Production of dielectric portions (138) covering, in the first openings (124), lateral flanks formed at least by the second layer (116);
    - second etching of the stack (106), extending the first openings (124) through a remaining thickness of the first layer (108) until reaching the substrate (104), the first openings (124) delimiting portions ( 130, 136) first and second layers (108, 116) forming pn junctions of the diodes (102);
    - etching extending the first openings (124) in a part of the substrate (104);
    - Production of first electrically conductive portions (148) disposed in the first openings (124) and in electrical contact with lateral flanks (140) of the portions (136) of the first layer (108), forming first electrodes of the diodes (102 ), and production of second electrodes (150) electrically connected to the portions (130) of the second layer (116);
    - Removal of the substrate (104), revealing a rear face (158) of each of the diodes (102) and releasing parts of the first electrically conductive portions (148) forming a collimation grid (160).
    Method according to Claim 1, in which the part of the substrate (104) in which the etching extending the first openings (124) is carried out has a thickness of between 1 µm and 20 µm and / or in which a ratio between the thickness of the part of the substrate (104) in
    which the etching extending the first openings (124) is implemented and a smaller dimension of each first opening (124) in a plane parallel to an interface between the substrate (104) and the stack (106) is greater than or equal to 2. [Claim 3] Method according to one of the preceding claims, in which:the first etching of the stack (106) is implemented such that the first openings (124) also pass through a part (134) of the first layer (108), and- the dielectric portions (138) are produced such that they cover, in the first openings (124), lateral flanks of said part (134) of the first layer (108). [Claim 4] Method according to one of the preceding claims, in which:the stack (106) comprises a dielectric mask forming the front face (122) of the stack (106),- The first and second etchings of the stack (106) are implemented through the dielectric mask (126) such that the first openings (124) also pass through the dielectric mask (126), and - the dielectric portions (138) also cover, in the first openings (124), lateral flanks of the dielectric mask (126). [Claim 5] The method of claim 4, wherein the second stacking etching (106) is performed such that lateral flanks of the dielectric portions (138) are aligned with the lateral flanks (140) of the portions (136) of the first layer (108). . [Claim 6] Method according to one of claims 4 or 5, further comprising, between the second stacking etching (106) and the production of the first electrically conductive portions (148), the production of second openings (142) passing through the dielectric mask (126 ) and in which the second electrodes (150) are at least partially produced. [Claim 7] Method according to claim 6, in which the first and second electrodes are produced by depositing at least one electrically conductive material (144, 146) in the first and second openings (124, 142) and on the dielectric mask (126), then in implementing a planarization step of the electrically conductive material (144, 146) with stopping on the dielectric mask (126). [Claim 8] Method according to one of the preceding claims, in which the stack (106) further comprises an electrically layer
    conductive (118) such that the second layer (116) is disposed between the electrically conductive layer (118) and the first layer (108), and in which the first etching of the stack (106) is implemented such that the first openings (124) pass through the electrically conductive layer (118) and define portions (128) of the electrically conductive layer (118) forming part of each of the second electrodes (150). [Claim 9] Method according to one of the preceding claims, further comprising, between the production of the first electrically conductive portions (148) and the removal of the substrate (104), the implementation of a postponement of the stack (106) and of the substrate (104) on a support (152) such that the stack (106) is disposed between the substrate (104) and the support (152). [Claim 10] The method of claim 9, wherein the transfer of the stack (106) and the substrate (104) is implemented with electrically conductive connection elements (154) electrically connecting the first and second electrodes of the diodes (102) to the support (152) during the implementation of the transfer of the stack (106) and the substrate (104) on the support (152). [Claim 11] Method according to one of claims 9 or 10, in which the step of removing the substrate (104) is carried out collectively for several devices (100) with light emitting diodes (102) and / or photoreceptors each comprising a stack ( 106) and a substrate (104) transferred onto a support (152), and in which the supports (152) of the photo-emitting and / or photo-receiving devices (100) with diodes (102) are secured on a retaining plate (200) before the implementation of the step of removing the substrate (104). [Claim 12] Method according to one of the preceding claims, in which the first openings (148) are made such that they form a grid pattern surrounding each of the diodes (102). [Claim 13] Method according to one of the preceding claims, in which the etching steps are carried out such as:each of the first openings (124) delimiting pn junctions of light-emitting diodes (102) has a smaller dimension, at the level of a bottom wall formed in the substrate (104), which is less than a smaller dimension the first opening (124) at an interface between the substrate (104) and the stack (106), and / oreach of the first openings (124) delimiting p-n junctions of
    photo-receiving diodes (102) have a smaller dimension at the bottom wall formed in the substrate (104) which is greater than the smallest dimension of the first opening (124) at the interface between the substrate (104) and the stack (106).
    [Claim 14] Method according to one of the preceding claims, further comprising, after the step of removing the substrate (104), the implementation of a step of depositing at least one anti-reflection layer and / or metallic on the collimation grid (160), and / or the implementation of a treatment increasing the roughness of the collimation grid (160).
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    同族专利:
    公开号 | 公开日
    CN111326613A|2020-06-23|
    EP3667728A1|2020-06-17|
    EP3667728B1|2021-03-31|
    US11063172B2|2021-07-13|
    US20200194614A1|2020-06-18|
    FR3090200B1|2021-01-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20120007133A1|2010-07-12|2012-01-12|Hyun Kyong Cho|Light emitting device and lighting system|
    WO2014105403A1|2012-12-31|2014-07-03|Invensas Corporation|High performance light emitting diode|
    EP3024030A1|2014-11-18|2016-05-25|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Optoelectronic device with light emitting diodes and method of manufacturing the same|
    WO2017068029A1|2015-10-22|2017-04-27|Commissariat A L'energie Atomique Et Aux Energies Alternatives|Microelectronic diode with optimised active surface|
    US6207532B1|1999-09-30|2001-03-27|Taiwan Semiconductor Manufacturing Company|STI process for improving isolation for deep sub-micron application|
    JP4241856B2|2006-06-29|2009-03-18|三洋電機株式会社|Semiconductor device and manufacturing method of semiconductor device|
    DE102007022947A1|2007-04-26|2008-10-30|Osram Opto Semiconductors Gmbh|Optoelectronic semiconductor body and method for producing such|
    US7998808B2|2008-03-21|2011-08-16|International Rectifier Corporation|Semiconductor device fabrication using spacers|
    JP5010660B2|2009-09-25|2012-08-29|株式会社東芝|Semiconductor device and manufacturing method thereof|
    DE102010025320B4|2010-06-28|2021-11-11|OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung|Optoelectronic component and method for its production|
    US8691661B2|2010-10-28|2014-04-08|Texas Instruments Incorporated|Trench with reduced silicon loss|
    DE102011016302A1|2011-04-07|2012-10-11|Osram Opto Semiconductors Gmbh|Optoelectronic semiconductor chip|
    US8791009B2|2011-06-07|2014-07-29|International Business Machines Corporation|Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via|
    DE102013103409A1|2013-04-05|2014-10-09|Osram Opto Semiconductors Gmbh|Optoelectronic semiconductor chip and optoelectronic module|CN108886050A|2017-01-24|2018-11-23|歌尔股份有限公司|Micro- LED matrix, display equipment and micro- LED manufacturing method|
    US11177397B2|2020-01-09|2021-11-16|Vanguard International Semiconductor Corporation|Semiconductor devices and methods for forming the same|
    US11158759B1|2020-04-16|2021-10-26|International Business Machines Corporation|Chip carrier integrating power harvesting and regulation diodes and fabrication thereof|
    CN111864016B|2020-06-30|2021-07-13|南京中电熊猫液晶显示科技有限公司|Manufacturing method of micro light-emitting diode|
    法律状态:
    2019-12-31| PLFP| Fee payment|Year of fee payment: 2 |
    2020-06-19| PLSC| Publication of the preliminary search report|Effective date: 20200619 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 3 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1872886A|FR3090200B1|2018-12-13|2018-12-13|PROCESS FOR MAKING A DEVICE WITH PHOTO-EMITTING AND / OR PHOTO-RECEIVING DIODES AND A SELF-ALIGNED COLLIMATION GRID|FR1872886A| FR3090200B1|2018-12-13|2018-12-13|PROCESS FOR MAKING A DEVICE WITH PHOTO-EMITTING AND / OR PHOTO-RECEIVING DIODES AND A SELF-ALIGNED COLLIMATION GRID|
    EP19213658.8A| EP3667728B1|2018-12-13|2019-12-04|Method for manufacturing a device with light-emitting and/or light-receiving diodes and with a self-aligned collimation grid|
    US16/705,428| US11063172B2|2018-12-13|2019-12-06|Method for producing a device with light emitting and/or light receiving diodes and with self-aligned collimation grid|
    CN201911281854.0A| CN111326613A|2018-12-13|2019-12-13|Method for producing a component having a light-emitting and/or light-receiving diode|
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